Job Details: Job Description: As an EDA Tools Hardware Engineer, you will play a pivotal role in advancing design automation and methodologies at Intel. Your contributions will directly impact cutting-edge semiconductor design, power and performance optimization, and the
Job Details: Job Description: Develop and integrate iterative timing closure flows for advanced APR (Automated Place and Route) in EDA tools to achieve PPA convergence on new process nodes/PDKs. Drive team to utilize and improve AI agents
Job Description Main responsibilities Work and lead junior engineer towards projects delivery with other layout and circuit design engineers to resolve any technical issues that will affect layout to ensure high quality. Utilize EDA tools (Cadence and Synopsys) for
ASIC Design Engineer 吉隆坡 全职 芯片板块 职位描述 ResponsibilitiesISP Module RTL DesignDesign and implement RTL for one or more blocks in the ISP pipeline (RAW / RGB / YUV domain, 3A statistics, geometric / scaling, etc.) under the
Senior Staff ASIC Design Engineer 吉隆坡 全职 芯片板块 职位描述 ResponsibilitiesISP Module / Sub-System OwnershipOwn the micro-architecture and RTL of key ISP blocks or sub-systems end-to-end, from spec definition through tape-out and mass production.Architecture & PPA LeadershipDrive pipeline-level
Job Details: Job Description: We are seeking a highly skilled Analog Layout Design Engineer to join our dynamic team. The successful candidate will be responsible for leading the FPGA physical design and layout of complex digital, analog
Job Details: Job Description: Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the physical design flow
Job Details: Job Description: Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the physical design flow
Job Details: Job Description: Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the physical design flow
Job Details: Job Description: As an STA design engineer candidate will be responsible for timing closure and signoff of FPGA/SoC and Subsystem timing. Candidate will be involved in static timing analysis, providing/deriving interface timing constraints to partitions
General Information Job Title Applications Engineering, Sr Engineer (RTL2GDS) Job ID 17645 Country Malaysia City Penang Date Posted 27-May-2026 Job Category Engineering Job Subcategory Applications Engineering Hire Type Employee Remote Eligible No Descriptions & Requirements Job Description
Job Details: Job Description: Job Description: We are seeking a highly experienced Signal Integrity & Power Integrity (SI/PI) Engineer with 8+ years of industry experience to lead the design, verification, and optimization of high‑speed interconnects across silicon,
Job Details: Job Description: Join Intel as a Physical Design Engineer and play a pivotal role in shaping the future of custom IP and SoC designs. In this position, you will be instrumental in transforming designs from
Job Details: Job Description: Seeking an experienced Hardware Board Design Engineer with 8+ years of expertise in designing and delivering complex hardware platforms. This role includes driving end-to-end development of platform hardware and translates platform-level requirements to
Job Details: Job Description: The DFT Architect at Altera is a senior technical authority responsible for defining, driving, and governing next‑generation DFT architecture across Altera’s most advanced FPGA, SoC, and multi‑die silicon platforms. This role sits
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Company Description We are committed to our culture that values Customer Focus, Flexibility, Knowledge, Speed and Integrity. Joining our team means you will work in a high performing global company where employees collaborate and strive for
About Bitdeer: Bitdeer is a world-leading technology company for Bitcoin mining and AI cloud. Bitdeer is committed to providing comprehensive Bitcoin mining solutions for its customers. Apart from designing industry-leading ASIC chips and manufacturing mining rigs,
Technical Lead responsible for managing engineering application platforms supporting the Hardware Platform Solutions (HPS) organization across 12 global Design Centres. This role serves as the bridge between Engineering and IT, ensuring critical engineering tools, development platforms,