Protocol Buffers Jobs In Malaysia - 2 Job Positions Available

ASIC Design Engineer 吉隆坡 全职 芯片板块 职位描述 ResponsibilitiesISP Module RTL DesignDesign and implement RTL for one or more blocks in the ISP pipeline (RAW / RGB / YUV domain, 3A statistics, geometric / scaling, etc.) under

Senior Staff ASIC Design Engineer 吉隆坡 全职 芯片板块 职位描述 ResponsibilitiesISP Module / Sub-System OwnershipOwn the micro-architecture and RTL of key ISP blocks or sub-systems end-to-end, from spec definition through tape-out and mass production.Architecture & PPA LeadershipDrive